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1/29 april 2000 n dmt modem for cpe adsl, compatible with the following standards: - ansi t1.413 issue 2 - itu-t g.992.1 (g.dmt) - itu-t g.992.2 (g.lite) n supports either atm (utopia level 1 & 2) or bitstream interface n 16 bit multiplexed microprocessor interface (little and big endian compatibility) n analog front end management n dual latency paths: fast and interleaved n atm's phy layer: cell processing (cell delineation, cell insertion, hec) n adsl's overhead management n reed solomon encode/decode n trellis encode/decode (viterbi) n dmt mapping/ demapping over 256 carriers n fine (2ppm) timing recover using rotor and adaptative frequency domain equalizing n time domain equalization n front end digital filters n 0.35 m m hcmos6 technology n 144 pin pqfp package n power consumption 1 watt at 3.3v applications routers at soho, stand-alone modems, pc modems general description the ST70135a is the dmt modem and atm framer of the stmicroelectronics ascot ? chipset. when coupled with st70134 analog front-end and an external controller running dedicated firmware, the product fulfills ansi t1.413 oissue 2o dmt adsl specification. the chip supports utopia level 1 and utopia level 2 interface and a non atm synchronous bit-stream interface. the ST70135a can be split up into two different sections. the physical one performs the dmt modulation, demodulation, reed-solomon encoding, bit interleaving and 4d trellis coding. the atm section embodies framing functions for the generic and atm transmission convergence (tc) layers. the generic tc consists of data scrambling and reed solomon error corrections, with and without interleaving. the ST70135a is controlled and programmed by an external controller (adsl transceiver controller, atc) that sets the programmable coefficients. the firmware controls the initialization phase and carries out the consequent adaptation operations. pqfp144 ordering number: ST70135a ST70135a ascot tm dmt transceiver
ST70135a 2/29 figure 1 : block diagram transient energy capabilities esd esd (electronic discharged) tests have been performed for the human body model (hbm) and for the charged device model (cdm). the pins of the device are to be able to withstand minimum 2000v for the hbm and minimum 250v for cdm. latch-up the maximum sink or source current from any pin is limited to 200ma to prevent latch-up. absolute maximum ratings test module data symbol timing unit vcxo dsp front-end fft/ifft rotor trellis coding generic tc interface module afe control controller atm test signals clock afe interface afe control controller bus general purpose i/os stm utopia mapper/ demapper reed/ solomon interface specific tc interface symbol parameter minimum typical maximum unit v dd supply voltage 3.0 3.3 3.6 v p tot total power dissipation 900 1400 mw t amb ambient temperature 1m/s airflow 0 70 c
ST70135a 3/29 figure 2 : pin connection 118 117 116 115 114 113 112 111 110 109 124 123 122 121 120 119 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 63 64 65 66 67 68 69 70 71 72 57 58 59 60 61 62 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 afrxd_1 afrxd_0 vdd pdown gp_out testse trstb vss tck vdd tms tdo tdi slt_frame_s slt_req_s vss vdd gp_in1 vss u_rx_refb u_tx_refb vdd u_rxclk u_rxsoc u_rxclav u_rxenbb vss u_txclk u_txsoc u_tx_clav u_txenbb vdd vdd slt_req_f slt_dat_s0 slt_dat_s1 slt_dat_f0 slt_dat_f1 vss slt_frame_f slat_clock slr_val_f slr_dat_f0 slr_dat_f1 slr_val_s vdd slr_dat_s0 slr_dat_s1 vss ad_0 ad_1 ad_2 vdd ad_3 ad_4 vss ad_5 ad_6 vdd ad_7 ad_8 ad_9 vss ad_10 ST70135a 134 133 132 131 130 129 128 127 126 125 140 139 138 137 136 135 aftxd_1 aftxd_0 iddq vdd aftxed_3 aftxed_2 vss aftxed_1 aftxed_0 vdd ctrldata mclk clwd vss afrxd_3 afrxd_2 144 143 142 141 vdd aftxd_3 aftxd_2 vss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ad_11 vdd ad_12 vss pclk vdd ad_13 ad_14 ad_15 vss be1 ale vdd csb wr_rdb rdyb 33 34 35 36 obc_type intb resetb vss 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 slr_frame_s vss slr_frame_f u_tx_addr_0 u_tx_addr_1 u_tx_addr_2 vdd u_tx_addr_3 u_tx_addr_4 u_tx_data_0 u_tx_data_1 vdd u_tx_data_2 u_tx_data_3 u_tx_data_4 u_tx_data_5 76 75 74 73 vdd u_tx_data_6 u_tx_data_7 vss 47 48 49 50 51 52 53 54 55 56 41 42 43 44 45 46 u_rxdata_2 u_rxdata_3 vdd u_rxdata_4 u_rxdata_5 vss u_rxdata_6 u_rxdata_7 vdd u_rx_addr_0 u_rx_addr_1 u_rx_addr_2 u_rx_addr_3 vss u_rx_addr_4 gp_in0 37 38 39 40 vdd u_rxdata_0 u_rxdata_1 vss
ST70135a 4/29 pin functions pin name type supply driver bs function 1 vss 0v ground 2 ad_0 b vdd bd8scr b data 0 3 ad_1 b vdd bd8scr b data 1 4 ad_2 b vdd bd8scr b address / data 2 5 vdd (vss + 3.3v) power supply 6 ad_3 b vdd bd8scr b address / data 3 7 ad_4 b vdd bd8scr b address / data 4 8 vss 0v ground 9 ad_5 b vdd bd8scr b address / data 5 10 ad_6 b vdd bd8scr b address / data 6 11 vdd (vss + 3.3v) power supply 12 ad_7 b vdd bd8scr b address / data 7 13 ad_8 b vdd bd8scr b address / data 8 14 ad_9 b vdd bd8scr b address / data 9 15 vss 0v ground 16 ad_10 b vdd bd8scr b address / data 10 17 ad_11 b vdd bd8scr b address / data 11 18 vdd (vss + 3.3v) power supply 19 ad_12 b vdd bd8scr b address / data 12 20 vss 0v ground 21 pclk i vdd ibuf i processor clock 22 vdd (vss + 3.3v) power supply 23 ad_13 b vdd bd8scr b address / data 13 24 ad_14 b vdd bd8scr b address / data 14 25 ad_15 b vdd bd8scr b address / data 15 26 vss 0v ground 27 be1 i vdd ibuf i address 1 28 ale i vdd ibuf c address latch 29 vdd (vss + 3.3v) power supply 30 csb i vdd ibuf i chip select 31 wr_rdb i vdd ibuf i specifies the direction of the access cycle 32 rdyb oz vdd bt4cr o controls the atc bus cycle termination 33 obc_type i-pd vdd ibuf i atc mode selection (0 = i960; 1 = generic) 34 intb o vdd ibuf o requests atc interrupt service 35 resetb i vdd ibuf i hard reset 36 vss 0v ground
ST70135a 5/29 37 vdd (vss + 3.3v) power supply 38 u_rxdata_0 oz vdd bd8src b utopia rx data 0 39 u_rxdata_1 oz vdd bd8src b utopia rx data 1 40 vss 0v ground 41 u_rxdata_2 oz vdd bd8src b utopia rx data 2 42 u_rxdata_3 oz vdd bd8src b utopia rx data 3 43 vdd (vss + 3.3v) power supply 44 u_rxdata_4 oz vdd bd8src b utopia rx data 4 45 u_rxdata_5 oz vdd bd8src b utopia rx data 5 46 vss 0v ground 47 u_rxdata_6 oz vdd bd8src b utopia rx data 6 48 u_rxdata_7 oz vdd bd8src b utopia rx data 7 49 vdd (vss + 3.3v) power supply 50 u_rxaddr_0 i vdd ibuf i utopia rx address 0 51 u_rxaddr_1 i vdd ibuf i utopia rx address 1 52 u_rxaddr_2 i vdd ibuf i utopia rx address 2 53 u_rxaddr_3 i vdd ibuf i utopia rx address 3 54 vss 0v ground 55 u_rxaddr_4 i vdd ibuf i utopia rx address 4 56 gp_in_0 i-pd vdd ibufdq i general purpose input 0 57 vdd (vss + 3.3v) power supply 58 gp_in_1 i-pd vdd ibufdq i general purpose input 1 59 vss 0v ground 60 u_rxrefb o vdd ibuf o 8khz clock to atm device 61 u_txrefb i vdd bt4cr i 8khz clock from atm device 62 vdd (vss + 3.3v) power supply 63 u_rx_clk i vdd ibuf utopia rx clock 64 u_rx_soc oz vdd bd8scr utopia rx start of cell 65 u_rxclav oz vdd bd8scr utopia rx cell available 66 u_rxenbb i vdd ibuf utopia rx enable 67 vss 0v ground 68 u_tx_clk i vdd ibuf utopia tx clock 69 u_tx_soc i vdd ibuf utopia tx start of cell 70 u_txclav oz vdd bd8scr utopia tx cell available 71 u_txenbb i vdd ibuf utopia tx enable 72 vdd (vss + 3.3v) power supply pin name type supply driver bs function pin functions (continued)
ST70135a 6/29 73 vss 0v ground 74 u_txdata_7 i vdd ibuf i utopia tx data 7 75 u_txdata_6 i vdd ibuf i utopia tx data 6 76 vdd (vss + 3.3v) power supply 77 u_txdata_5 i vdd ibuf i utopia tx data 5 78 u_txdata_4 i vdd ibuf i utopia tx data 4 79 u_txdata_3 i vdd ibuf i utopia tx data 3 80 u_txdata_2 i vdd ibuf i utopia tx data 2 81 vdd (vss + 3.3v) power supply 82 u_txdata_1 i vdd ibuf i utopia tx data 1 83 u_txdata_0 i vdd ibuf i utopia tx data 0 84 u_txaddr_4 i vdd ibuf i utopia tx address 4 85 u_txaddr_3 i vdd ibuf i utopia tx address 3 86 vdd (vss + 3.3v) power supply 87 u_txaddr_2 i vdd ibuf i utopia tx address 2 88 u_txaddr_1 i vdd ibuf i utopia tx address 1 89 u_txaddr_0 i vdd ibuf i utopia tx address 0 90 slr_ frame_f o vdd bt4cr frame identifier fast 91 vss 0v ground 92 slr_frame_s o vdd bt4cr receive frame identifier interleaved 93 slr_data_s_1 o vdd bt4cr receive data interleave 1 94 slr_data_s_0 o vdd bt4cr receive data interleave 0 95 vdd (vss + 3.3v) power supply 96 slr_val_s o vdd bt4cr receive data valid indicator interleaved 97 slr_data_f_1 o vdd bt4cr receive data fast 1 98 slr_data_f_0 o vdd bt4cr receive data fast 0 99 slr_val_f o vdd bt4cr receive data valid indicator fast 100 slap_clock o vdd bt4cr clock for slap i/f 101 slt_frame_f o vdd bt4cr transmit start of frame indicator fast 102 vss 0v ground 103 slt_data_f_1 i vdd ibufdq transmit data fast 1 104 slt_data_f_0 i vdd ibufdq transmit data fast 0 105 slt_data_s_1 i vdd ibufdq transmit data interleave 1 106 slt_data_s_0 i vdd ibufdq transmit data interleave 0 107 slt_req_f o vdd bt4cr transmit byte request fast 108 vdd (vss + 3.3v) power supply pin name type supply driver bs function pin functions (continued)
ST70135a 7/29 109 vss 0v ground 110 slt_req_s o vdd bt4cr transmit byte request interleaved 111 stl_frame_s o vdd bt4cr transmit start of frame indication interleaved 112 tdi i-pu vdd ibufuq jtag i/p 113 tdo oz vdd bt4cr jtag o/p 114 tms i-pu vdd ibufuq jtag made select 115 vdd (vss + 3.3v) power supply 116 tck i-pd vdd ibufdq jtag clock 117 vss 0v ground 118 trstb i-pd vdd ibufdq jtag reset 119 testse i vdd ibuf none enables scan test mode 120 gp_out o vdd bd8scr o general purpose output 121 pdown o vdd bt4cr o power down analog front end (reset) 122 vdd (vss + 3.3v) power supply 123 afrxd_0 i vdd ibuf i receive data nibble 124 afrxd_1 i vdd ibuf i receive data nibble 125 afrxd_2 i vdd ibuf i receive data nibble 126 afrxd_3 i vdd ibuf i receive data nibble 127 vss 0v ground 128 clwd i vdd ibuf i start of word indication 129 mclk i vdd ibuf c master clock 130 ctrldata o vdd bt4cr o serial data transmit channel 131 vdd (vss + 3.3v) power supply 132 aftxed_0 o vdd bt4cr o transmit echo nibble 133 aftxed_1 o vdd bt4cr o transmit echo nibble 134 vss 0v ground 135 aftxed_2 o vdd bt4cr o transmit echo nibble 136 aftxed_3 o vdd bt4cr o transmit echo nibble 137 vdd (vss + 3.3v) power supply 138 iddq i vdd ibuf none test pin, active high 139 aftxd_0 o vdd bt4cr o transmit data nibble 140 aftxd_1 o vdd bt4cr o transmit data nibble 141 vss 0v ground 142 aftxd_2 o vdd bt4cr o transmit data nibble 143 aftxd_3 o vdd bt4cr o transmit data nibble 144 vdd (vss + 3.3v) power supply pin name type supply driver bs function pin functions (continued)
ST70135a 8/29 i/o driver function pin summary driver function bd4cr cmos bidirectional, 4ma, slew rate control bd8scr cmos bidirectional, 8ma, slew rate control, schmitt trigger ibuf cmos input ibufdq cmos input, pull down, iddq control ibufuq cmos input, pull up, iddq control mnemonic type bs type signals function power supply vdd (vss + 3.3v) power supply vss 0v ground atc interface ale i c 1 used to latch the address of the internal register to be accessed pclk i i 1 processor clock csb i i 1 chip selected to respond to bus cycle be1 i i 1 address 1 (not multiplexed) wr_rdb i i 1 specifies the direction of the access cycle rdyb oz o 1 controls the atc bus cycle termination intb o o 1 requests atc interrupt service ad io b 16 multiplexed address/data bus obc_type i-pd i 1 select between i960 (0) or generic (1) controller interface test access part interface tdi i-pu 1 refer to section tdo oz 1 tck i-pd 1 tms i-pu 1 trstb i-pd 1 analog front end interface afrxd i i 4 receive data nibble aftxd o o 4 transmit data nibble aftxed o o 4 transmit echo nibble clwd i i 1 start of word indication pdown o o 1 power down analog front end ctrldata o o 1 serial data transmit channel mclk i c 1 master cloc
ST70135a 9/29 atm utopia interface u_rxdata oz b 8 receive interface data u_txdata i i 8 transmit interface data u_rxaddr i i 5 receive interface address u_txaddr i i 5 transmit interface address u_rxclav oz o 1 receive interface cell available u_txclav oz o 1 transmit interface cell available u_rxenbb i-ttl i 1 receive interface enable u_txenbb i-ttl i 1 transmit interface enable u_rxsoc oz o 1 receive interface start of cell u_txsoc i-ttl i 1 transmit interface start of cell u_rxclk i-ttl c 1 receive interface utopia clock u_txclk i-ttl c 1 transmit interface utopia clock u_rxrefb o o 1 8khz reference clock to atm device u_txrefb i-ttl i 1 8khz reference clock from atm device atm slap interface slr_val_s o 1 slr_val_f o 1 slr_data_s o 2 slr_data_f o 2 slt_req_s o 1 slt_req_f o 1 slt_data_s i 2 slt_data_f i 2 slap_clock o 1 slr_frame_i o 1 slt_frame_i o 1 slr_frame_f o 1 slt_frame_f o 1 miscellaneous gp_in i-pd i 2 general purpose input gp_out o o 1 general purpose output resetb i i i hard reset testse i none none enable scan test mode iddq i none none test pin, active high mnemonic type bs type signals function
ST70135a 10/29 i = input, cmos levels i-pu = input with pull-up resistance, cmos levels i-pd = input with pull-down resistance, cmos levels i-ttl = input ttl levels o = push-pull output oz = push-pull output with high-impedance state io = input / tristate push-pull output bs cell = boundary-scan cell i = input cell o = output cell b = bidirectional cell c = clock main block description the following drawings describe the sequence of functions performed by the chip. dsp front-end the dsp front-end contains 4 parts in the receive direction: the input selector, the analog front-end interface, the decimator and the time equalizer. the input selector is used internally to enable test loopbacks inside the chip. the analog front-end lnterface transfers 16-bit words, multiplexed on 4 input/output signals. word transfer is carried out in 4 clock cycles. the decimator receives 16-bit samples at 8.8mhz (as sent by the analog front-end chip: st70134) and reduces this rate to 2.2mhz. the time equalizer (teq) module is a fir filter with programmable coefficients. its main purpose is to reduce the effect of inter-symbol interferences (isi) by shortening the channel impulse response. both the decimator and teq can be bypassed. in the transmit direction, the dsp front-end includes: sidelobe filtering, clipping, delay equalization and interpolation. the sidelobe filtering and delay equalization are implemented by iir filters, reducing the effect of echo in fdm systems. clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the afe. the interpolator receives data at 2.2mhz and generates samples at a rate of 8.8mhz. dmt modem this module is a programmable dsp unit. its instruction set enables the basic functions of the dmt algorithm like fft, ifft, scaling, rotor and frequency equalization (feq) in compliance with ansi t1.413 specifications. in the rx path, the 512-point fft transforms the time-domain dmt symbol into a frequency domain representation which can be further decoded by the subsequent demapping stages. in other words, the fast fourier transform process is used to transform from time domain to frequency domain (receive path). 1024 time samples are processed. after the first stage time domain equalization and fft block an ici (intercarrier interference) free information stream turns out. figure 3 : dsp front-end receive figure 4 : dsp front-end transmit from analog front-end in select afe i/f dec tec bypass to dmt modem from dmt modem filtering clipping afe i/f to analog front end delay equalizer out select inter- polator
ST70135a 11/29 this stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. to compensate, a frequency domain equalizer (feq) and a rotor (phase shifter) are implemented. the frequency domain equalization performs an operation on the received vector in order to match it with the associated point in the constellation. the coefficient used to perform the equalization are floating point, and may be updated by hardware or software, using a mechanism of active and inactive table to avoid dmt synchro problems.in the transmit path, the ifft reverses the dmt symbol from frequency domain to time domain. the ifft block is preceded by fine tune gain (ftg) and rotor stages, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). the inverse fast fourier transform process is used to transform from frequency domain to time domain (transmit path). 256 positive frequencies are processed, giving 512 samples in the time domain. the fft module is a slave dsp engine controlled by the firmware running on an external controller. it works off line and communicates with other blocks through buffers controlled by the odata symbol timing unito. the dsp executes a program stored in a ram area, which constitutes a flexible element that allows for future system enhancements. dpll the digital pll module receives a metric for the phase error of the pilot tone. in general, the clock frequencies at the ends (transmitter and receiver) do not match exactly. the phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. various processes can use this estimate to deal with the frequency mismatch. in particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (rotor). larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. eventually that leads to achieve less than 2ppm between the two ends. mapper/demapper, monitor, trellis coding, feq update the demapper converts the constellation points computed by the fft to a block of bits. this means to identify a point in a 2d qam constellation plane. the demapper supports trellis coded demodulation and provides a viterbi maximum likelihood estimator. when the trellis is active, the demapper receives an indication for the most likely constellation subset to be used. figure 5 : dmt modem (rx & tx) to/from dsp fe fft ifft feq ftg mapper demapper rotor to/from treillis coding decoding monitor feq coefficients feq update monitor indications tc
ST70135a 12/29 in the transmit direction, the mapper receives a bit stream from the trellis encoder and modulates the bit stream on a set of carriers (up to 256). it generates coordinates for 2n qam constellation, where n < 15 for all carriers. the mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the ifft block. the trellis encoder generates redundant bits to improve the robustness of the transmission, using a 4-dimensional trellis coded modulation scheme. this feature can be disabled.the monitor computes error parameters for carriers specified in the demapper process. those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc. a series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. generic tc layer functions these functions relate to byte oriented data streams. they are completely described in ansi t 1.4 13. additions described in the issue 2 of this specification are also supported. the data received from the demapper may be split into two paths, one dedicated to an interleaved data flow the other one for a fast data flow. no external ram is needed for the interleaved path. the interleaving/deinterleaving is used to increase the error correcting capability of block codes for error bursts. after deinterleaving (if applicable), the data flow enters a reed-solomon error correcting code decoder, able to correct a number of bytes containing bit errors. the decoder also uses the information of previous receiving stages that may have detected the error bytes and have labelled them with an oerasure indicationo. each time the rs decoder detects and corrects errors in a rs codeword, an rs correction event is generated. the occurrence of such events can be signalled to the management layer.after the rs decoder, the corrected byte stream is descrambled in the pmd (physical medium dependent) descramblers. two descramblers are used, for interleaved and non-interleaved data flows. these are defined in ansi t1.413. after descrambling, the data flows enter the deframer that extracts and processes bytes to support physical layer related functions according to ansi t1.413. the adsl frames indeed contain physical layer-related information in addition to the data passed to the higher layers. in particular, the deframer extracts the eoc (embedded operations channel), the aoc (adsl overhead control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). the deframer also performs a crc check (cyclic redundancy check) on the received frame and generates events in case of error detection.event counters can be read by management processes. the outputs of the deframer are an interleaved and a fast data streams. these data streams can either carry atm cells or another type of traffic. in the latter case, the atm specific tc layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the interface module. figure 6 : generic tc layer functions data patx merger interleaver de-interleaver rs coding pmd scrambler pmd scrambler decoding f i framer deframer f i to atm tc indicationbits aoc eoc to/from demapper fast descrambler descrambler
ST70135a 13/29 atm specific tc layer functions the 2 bytes streams (fast and slow) are received from the byte-based processing unit. when atm cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell header error correction (hec) and detection. the cell processing happens according to itu-t i.163 standard. provision is also made for ber measurements at this atm cell level. when non cell oriented byte streams are transported, the cell processing unit is not active. the interface module collects cells (from the cell-based function module) or a byte stream (from the deframer). cells are stored in fifo's (424 bytes or 8 cell wide, transmit buffers have the same size), from which they are extracted by 2 interface submodules, one providing a utopia level 1 interface and the other a utopia level 2 interface.byte stream are dumped on the slap (synchronous link access protocol) interface. only one type of interface can be enabled in a specific configuration. figure 7 : atm specific tc layer functions figure 8 : interface module cell scrambler descrambler synchronizer cell scrambler descrambler synchronizer hec hec cell insertion/ filter cell insertion/ filter ber ber fast slow to interface module from generic tc slap level 1 utopia level 2 utopia level 1 utopia level 2 utopia slap fast atm fast byte stream slow atm slow byte stream from atm tc
ST70135a 14/29 dmt symbol timing unit (dstu) the dstu interfaces with various modules, like dsp frontend, fft/ifft, mapper/demapper, rs, monitor and transceiver controller. it consists of a real time and a scheduler modules. the real time unit generates a timebase for the dmt symbols (sample counter), superframes (symbol counter) and hyper-frames (sync counter). the timebases can be modified by various control features. they are continuously fine-tuned by the dpll module. the dstu schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters. the transmit and receive sequencers are completely independent and run different programs. an independent set of variables is assigned to each of them. the sequencer programs can be updated in real time. ST70135a interfaces overview see figure 9. processor interface (atc) the ST70135a is controlled and configured by an external processor across the processor interface. all programmable coefficients and parameters are loaded through this path. data and addresses are multiplexed ST70135a works in 16 bits data access, so address bit 0 is not used. address bit 1 is not multiplexed with data. it has its own pin : be1. byte access are not supported. access cycle read or write are always in 16 bits data wide, ie bit address a0 is always zero value. the interrupt request pin to the processor is intb, and is an open drain output. the ST70135a supports both little and big endian. the default feature is big endian. generic interface this interface is suitable for a number of processors using a multiplexed address/data bus. in this case, synchronization of the input signals with pclk pin is not necessary. figure 9 : ST70135a interfaces afe interface to adsl line (st70134) reset jtag clock processor interface (atc) digital interface utopia/bitstream interface ST70135a figure 10 : generic processor interface write timing cycle t alew twr2cs t avs t avh t ale2cs t wr2d t wdvd t dvh t cs2rdy t cs2wr t wrw t mclk t csre t rdy2wr ale csb ad(15-0) wrb ready rdb
ST70135a 15/29 figure 11 : generic processor interface read timing cycle generic processor interface cycle timing all ac characteristics are indicated for a 100pf capacitive load. symbol parameters minimum typical maximum unit tr & tf rise & fall time (10% to 90%) 3 ns talew ale pulse width 12 ns tavs address valid setup time 10 ns tavh address valid hold time 10 ns tale2cs ale to csb 0 ns tale2z ale to high z state of address bus 50 ns tcs2rdy csb to rdyb asserted 60 ns tcsre access time 900 ms tcs2wr csb to wrb 0 ns twr2d wrb to data 15 ns trdy2wr rdyb to wrb 0 ns tdvs data setup time 10 ns tdvh data hold time 1/2tmclk tmclk ns twr2cs wrb to csb -10 ns tcs2rd csb to rdb 0 ns trdy2rd rdy to rdb 0 ns trd2cs rdb to csb -10 ns tmclk master clock timing t alew trd2cs t avs t avh t ale2cs t wr2d t wdvd t dvh t csrd t csrs t wrw t mclk t csre t rdy2dr ale csb ad(15-0) rdb ready wrb t ale2z
ST70135a 16/29 generic processor interface pins and functional description digital interface atm or serial digital interface for data to the loop before modulation and from the loop after demodulation. this interface collects cells (from the cell based function module) or a byte stream (from the deframer). cells are stored in a fifo, 2 interfaces submodules can extract data from the fifo. byte streams are dumped on the bitstream interface (with no fifo). 3 kinds of interface are allowed: utopia level 1 utopia level 2 bitstream based on a proprietary exchange the interface selection is programmed by writing the utopia phy address register. only one interface can be enabled in a ST70135a configuration. utopia level 1 supports only one phy device. utopia level 2 supports multi-phy devices (see utopia level 2 specifications). each buffer provides storage for 8 atm cells (both directions for fast and interleaved channel). the utopia level 2 supports point to multipoint configurations by introducing an addressing capability and by making distinction between polling and selecting a device. figure 12 : receive interface utopia level 1 interface the atm forum takes the atm layer chip as a reference. it defines the direction from atm to physical layer as the transmit direction. the direction from physical layer to atm is the receive direction. figures 12 & 13 show the interconnection between atm and phy layer devices, the optional signals are not supported and not shown. the utopia interface transfers one byte in a single clock cycle, as a result cells are transformed in 53 clock cycles. both transmit and receive are synchronized on clocks generated by the atm layer chip, and no specific relationship between receive and transmit clocks is required. in this mode, the ST70135a can only support one data flow : either interleaved or fast. name type function ad[0..15] i/o multiplexed address / data bus ale i address latch enable rdb i read cycle indication wrb i write cycle indication csb i chip select rdyb oz bus cycle ready indication intb o interrupt figure 13 : transmit interface phy receive rxref* rxclav rxenb* rxclk rxdata rxsoc cell receive phy atm 8 phy transmit txref* txclav txenb* txclk txdata txsoc cell transmit phy atm layer 8
ST70135a 17/29 figure 14 : timing (utopia 1 receive interface) pin description note 1. active low signal when rxenb is asserted, the ST70135a reads data from its internal fifo and presents it on rxdata and rxsoc on each low-to-high transition of rxclk, ie the atm layer chip samples all rxdata and rxsoc on the rising edge of rxsoc on the rising edge of rxclk. pin description note 1. active low signal name type meaning usage remark rxclav o receive cell available signals to the atm chip that the ST70135a has a cell ready for transfer remains active for the entire cell transfer rxenb 1 i receive enable signals to the ST70135a that the atm chip will sample and accept data during next clock cycle rxdata and rxsoc could be tri-state when rxenb* is inactive (high). active low signal rxclk i receive byte clock gives the timing signal for the transfer, generated by atm layer chip. rxdata o receive data (8bits) atm cell data, from ST70135a chip to atm chip, byte wide. rx data [7] is the msb. rxsoc o receive start cell identifies the cell boundary on rxdata indicate to the atm layer chip that rxdata contains the first valid byte of a cell. rxref 1 o reference clock 8 khz clock transported over the network active low signal name type meaning usage remark txclav o transmit cell available signals to the atm chip that the physical layer chip is ready to accept a complete cell remains active for the entire cell transfer txenb 1 i transmit enable signals to the ST70135a that txdata and txsoc are valid txclk i transmit byte clock gives the timing signal for the transfer, generated by atm layer chip. txdata i transmit data (8bits) atm cell data, from atm layer chip to ST70135a, byte wide. txdata [7] is the msb. txsoc i transmit start of cell identifies the cell boundary on txdata txdata contains the first valid byte of the cell. txref 1 i reference clock 8khz clock from the atm layer chip rxclk rxsoc rxenb x h1 h2 p44 p45 p47 p48 x p46 rxdata rxclav
ST70135a 18/29 the ST70135a samples txdata and txsoc signals on the rising edge of txclk, if txenb is asserted. txclk, rxclk, ac electrical characteristics txdata, txsoc, ac electrical characteristics rxdata, rxsoc, rxclav ac electrical characteristics symbol parameters min max unit f clock frequency 1.5 25 mhz tc clock duty cycle 40 60 % tj clock peak to peak jitter 5% trf clock rise fall time 4 ns l load 100 pf symbol parameters min max unit t5 input set-up time to txclk 10 ns t6 hold time to txclk 1 ns l load 100 pf symbol parameters min max unit t7 input set-up time to txclk 10 ns t8 hold time to tx clk 1 ns t9 signal going low impedance to rxclk 10 ns t10 signal going high impedance to rxclk 0ns t11 signal going low impedance to rxclk 1ns t12 signal going high impedance to rxclk 1ns l load 100 pf figure 15 : timing (utopia 1 transmit interface) figure 16 : timing specification (utopia 1) x h1 h2 p44 p45 p47 p48 x p46 txclk txsoc txenb txdata txclav clock signal (at input) signal (highz) t5, t7 t6, t8 t11 t9 t12 t10
ST70135a 19/29 digital interface utopia level 2 interface the atm forum takes the atm layer chip as a reference. it defines the direction from atm to physical layer as the transmit direction. the direction from physical layer to atm is the receive direction. figure 17 shows the interconnection between atm and phy layer devices, the optional signals are not supported and not shown. the utopia interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles.both transmit and receive interfaces are synchronized on clocks generated by the atm layer chip, and no specific relationship between receive and transmit clock is assumed, they must be regarded as mutually asynchronous clocks. flow control signals are available to match the bandwidth constraints of the physical layer and the atm layer. the utopia level 2 supports point to multipoint configurations by introducing on addressing capability and by making a distinction between polling and selecting a device: the atm chip polls a specific physical layer chip by putting its address on the address bus when the enb* line is asserted. the addressed physi- cal layer answers the next cycle via the clav line reflecting its status at that time. the atm chip selects a specific physical layer by putting its address on the address bus when the enb* line is deasserted and asserting the enb* line on the next cycle. the addressed physical layer chip will be the target or source of the next cell transfer (see figure 17). utopia level 2 signals the physical chip sends cell data towards the atm layer chip. the atm layer chip polls the status of the fifo of the physical layer chip. the cell exchange proceeds like: a) the physical layer chip signals the availability of a cell by asserting rxclav when polled by the atm chip. b) the atm chips selects a physical layer chip, then starts the transfer by asserting rxenb*. c) if the physical layer chip has data to send, it puts them on the rxdata line the cycle after it sampled rxenb* active. it also advances the offset in the cell. if the data transferred is the first byte of a cell, rxsoc is 1b at the time of the data transfer, 0b otherwise. d) the atm chip accepts the data when they are available. if rxsoc was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. ST70135a utopia level 2 mphy operation utopia level 2 mphy operation can be done by various interface schemes. the ST70135a supports only the required mode, this mode is referred to as ooperation with 1 txclav and 1 rxclavo. phy device identification the ST70135a holds 2 phy layer utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. the associated phy address is specified by the phy_addr_x fields in the utopia phy address register. figure 17 : signal at utopia level 2 interface phy receive rxaddr rxclav rxenb* rxclk rxdata rxsoc phy atm 8 5 rxref* atm receive phy transmit txaddr txclav txenb* txclk txdata txsoc 8 5 txref* atm transmit 1 1
ST70135a 20/29 beware that an incorrect address configuration may lead to bus conflicts. a feature is defined to disable (tri-state) all outputs of the utopia interface. it is enabled by the tri_state_en bit in the rx_interface control register. pin description utopia 2 (receive interface) *active low signal pin description utopia 2 (transmit interface) *active low signal name type meaning usage remark rxclav o receive cell available signals to the atm chip that the stlc60135 has a cell ready for transfer remains active for the entire cell transfer rxenb* i receive enable signals to the physical layer that the atm chip will sample and accept data during next clock cycle rxdata and rxsoc could be tri-state when rxenb* is inactive (high) rxclk i receive byte clock gives the timing signal for the transfer, generated by atm layer chip. rxdata o receive data (8 bits) atm cell data, from physical layer chip to atm chip, byte wide. rxsoc o receive start cell identifies the cell boundary on rxdata indicate to the atm layer chip that rxdata contains the first valid byte of a cell. rxaddr i receive address (5 bits) use to select the port that will be active or polled rxref * o reference clock 8khz clock transported over the network name type meaning usage remark txclav o transmit cell available signals to the atm chip that the physical layer chip is ready to accept a cell remains active for the entire cell transfer txenb* i transmit enable signals to the physical layer that txdata and txsoc are valid txclk i transmit byte clock gives the timing signal for the transfer, generated by atm layer chip. txdata i transmit data (8 bits) atm cell data, to physical layer chip to atm chip, byte wide. txsoc i transmit start of cell identifies the cell boundary on txdata txaddr i transmit address (5 bits) use to select the port that will be active or polled txref * i reference clock 8khz clock from the atm layer chip
ST70135a 21/29 bitstream interface the bitstream interface is a proprietary point to point interface. the ST70135a is the bus master of the interface. the interface is synchronous, a common clock is used. slap (synchronous link access protocol) interface the slap interface is a point to point bitstream interface. the ST70135a is the bus master of the interface. the interface is synchronous, a common clock (slap_clock) is used. the basic idea is illustrated in figure 17. the slap interface dumps the data of the fast and interleaved channels on 2 separate sub interfaces. the data flow from the slap interface must be enabled by the transceiver controller. a disabled cell interface does not dump data on its interface. receive slap interface the interface signals use 2 signal types: (refer to figure 19) slr_data [1:0]: data pins, a byte is transferred in 4 cycles of 2 bits. the msb are transmitted first, odd bits are asserted on slr_data [1]. slr_val: indicates the data transfer and the byte boundary slr_frame: indicates the start of a super- frame notice 2 slap interfaces are supported, one for the fast data flow, the other one for the interleaved data flow. the logic timing diagram is shown in figure 20. figure 18 : common clock data transfer dq ck qn source rising clock dq ck qn falling clock sink slap_clock figure 19 : receive path, slap interface external slap_clock component (slave) modem (master) data 2 valid frame figure 20 : receive slap interface timing one byte as 4 times 2 bits 0123 8 minimum 8 cycles stm_clock undefined undefined frame valid slr_val must not repeat in a 8 clock period b5 b3 b1 b4 b2 b0 b7 b6 slr_data(1) slr_data(0)
ST70135a 22/29 the implementation must guarantee that all active slr_valid signals must be separated by at least 8 clock cycles. refer to figure 20. the slr_frame signals are asserted when the first pair of bits of a frame are transferred. for the fast channel a frame is defined as a superframe timebase. for the interleaved channel the frame is defined by a timebase period of 4 superframes. both timebases are synchronized to the data flow. transmit slap interface the transmit interface uses the following signals (refer to figure 21): slt_req: byte request. slt_frame: start of frame indication. slt_data [1:0] data pins, a byte is transferred 2 bits at the time in 4 successive clock cycles. msb first, odd bits on slt_data [1]. the logical timing diagram is shown in figure 22. the delay between request and the associated data byte is defined as 8 cycles. the slt_frame signals are asserted when the first pair of bits of a frame are transferred. for the fast channel a frame is defined as a superframe timebase. for the interleaved channel the frame is defined by a timebase period of 4 superframes. both timebases are synchronized to the data flow and guarantee that the frame indication is asserted when the first bits of the first dmt symbol are transferred. slap interface, ac electrical characteristics figure 21 : interface towards phy layer figure 22 : interface timing external clock component (slave) modem (master) request 2 data frame t per t h t l t hd t s t d clock all inputs all outputs figure 23 : transmit slap interface timing diagram symbol parameter test conditi on minimum typical maximum unit t per clock period refer to mclk ns t h clock high 11 ns t l clock low 11 ns t s setup 3 ns t hd hold 2 ns t d data delay 20pf load 3 6 ns one byte in 4 cycles 01 89 1 clock undefined undefined request may be repeated b5 b3 b1 b4 b2 b0 b7 b6 slt_data(0) slt_frame 1 0 1 2 after 4 cycles delay request-data equals 8 cycles repeated each superframe/ s-frame stm_clock slt_data(1) slt_request
ST70135a 23/29 analog front end control interface the analog front end interface is designed to be connected to the st70134 analog front end component. transmit interface the 16 bit words are multiplexed on 4 aftxd output signals. as a result 4 cycles are needed to transfer 1 word. refer to table 1 for the bit/pin allocation for the 4 cycles. the first of 4 cycles is identified by the clwd signal. refer to figure 23. the ST70135a fetches the 16 bit word to be multiplexed on aftxd from the tx digital front-end module. receive interface the 16 bit receive word is multiplexed on 4 afrxd input signals. as a result 4 cycles are needed to transfer 1 word. refer to table 2 for the bit / pin allocation for the 4 cycles. the first of 4 cycles is identified by the clwd must repeat after 4 mclk cycles. figure 24 : transmit word timing diagram figure 25 : receive word timing diagram cycle1 cycle0 cycle2 cycle3 test0 test1 test2 test3 mclk clwd aftxd aftxed gp_out cycle1 cycle0 cycle2 cycle3 test0 test1 test2 test3 mclk clwd afrxd gp_in(0)
ST70135a 24/29 figure 26 : transmit interface table 1 : transmitted bits assigned to signal / time slot figure 27 : receive interface mclk aftxd clwd tv tc aftxed mclk afrxd ts th cycle 0 cycle 1 cycle 2 cycle 3 aftxd[0] b0 b4 b8 b12 aftxd[1] b1 b5 b9 b13 aftxd[2] b2 b6 b10 b14 aftxd[3] b3 b7 b11 b15 gp_out t0 t1 t2 t3 table 2 : transmitted bits assigned to signal / time slot cycle 0 cycle 1 cycle 2 cycle 3 afrxd[0] b0 b4 b8 b12 afrxd[1] b1 b5 b9 b13 afrxd[2] b2 b6 b10 b14 afrxd[3] b3 b7 b11 b15 gp_in t0 t1 t2 t3 table 3 : master clock (mclk) ac electrical characteristics symbol parameter minimum typical maximum unit f clock frequency 35.328 mhz tper clock period 28.3 ns th clock duty cycle 40 60 % table 4 : aftxd, aftxed, clwd ac electrical characteristics symbol parameter minimum typical maximum unit tv data valid time 0 10 ns tc data valid time 0 10 ns table 5 : afrxd ac electrical characteristics symbol parameter minimum typical maximum unit ts data setup time 5 ns th data hold time 5 ns
ST70135a 25/29 tests, clock, jtag interface mclk: master clock (35.328mhz) generated by vcxo atm receive interface, asynchronous clock gen- erated by utopia master atm transmit interface, asynchronous clock generated by utopia master atc clock (pclk): external asynchronous clock (synchronous with atc in case of i960 specific interface) jtag tp interface: standard test access port, used with the boundary scan for chip and board testing. this jtag tap interface consists in 5 signals: tdi, tdo, tck & tms. tsrtb: test reset, reset the tap controller. trstb is an active low signal. table 6 : boundary scan chain sequence sequence number mnemonic pin bs type 2 ad_0 b 3 ad_1 b 4 ad_2 b 6 ad_3 b 7 ad_4 b 9 ad_5 b 10 ad_6 b 12 ad_7 b 13 ad_8 b 14 ad_9 b 16 ad_10 b 17 ad_11 b 19 ad_12 b 21 pclk i 23 ad_13 b 24 ad_14 b 25 ad_15 b 27 be1 i 28 ale c 30 csb i 31 wr_rdb i 32 rdyb o 33 obc_type i 34 intb o 35 resetb i 38 u_rxdata_0 b 39 u_rxdata_1 b 41 u_rxdata_2 b 42 u_rxdata_3 b 44 u_rxdata_4 b 45 u_rxdata_5 b 46 vss 47 u_rxdata_6 b 48 u_rxdata_7 b 50 u_rxaddr_0 i 51 u_rxaddr_1 i 52 u_rxaddr_2 i 53 u_rxaddr_3 i 55 u_rxaddr_4 i 56 gp_in_0 i 58 gp_in_1 i 60 u_rxrefb o 61 u_txrefb i 63 u_rxclk 64 u_rxsoc 65 u_rxclav 66 u_rxenbb 68 u_txclk 69 u_txsoc 70 u_txclav 71 u_txenbb 74 u_txdata_7 i 75 u_txdata_6 i 77 u_txdata_5 i 78 u_txdata_4 i 79 u_txdata_3 i 80 u_txdata_2 i 82 u_txdata_1 i table 6 : boundary scan chain sequence sequence number mnemonic pin bs type
ST70135a 26/29 general purpose i/o register 2 general purpose register (0x040) bits from 3 to 15 are reserved reset initialization the ST70135a supports two reset modes: a 'hardware' reset is activated by the resetb pin (active low). a hard reset occurs when a low input value is detected at the resetb input. the low level must be applied for at least 1ms to guarantee a correct reset operation. all clocks and power supplies must be stable for 200ns prior to the rising edge of the resetb signal. 'soft' reset activated by the controller write access to a soft reset configuration bit. the reset process takes less than 10000 mclk clock cycles. 83 u_txdata_0 i 84 u_txaddr_4 i 85 u_txaddr_3 i 87 u_txaddr_2 i 88 u_txaddr_1 i 89 u_txaddr_0 i 90 slr_frame_f 92 slr_frame_s 93 slr_data_s_1 94 slr_data_s_0 96 slr_data_s 97 slr_data_f_1 98 slr_data_f_0 99 slr_val_f 100 slap_clock 101 slt_frame_f 103 slt_data_f_1 104 slt_data_f_0 105 slt_data_s_1 106 slt_data_s_0 107 slt_req_f 110 slt_req_s 111 slt_frame_s 112 tdi 113 tdo 114 tms 116 tck 118 trstb 119 testse none 120 gp_out o 121 pdown o 123 afrxd_0 i 124 afrxd_1 i 125 afrxd_2 i table 6 : boundary scan chain sequence sequence number mnemonic pin bs type 126 afrxd_3 i 128 clwd 1 i 129 mclk 1 c 130 ctrldata 1 o 132 aftxed_0 o 133 aftxed_1 o 135 aftxed_2 o 136 aftxed_3 o 138 iddq none 139 aftxd_0 o 140 aftxd_1 o 142 aftxd_2 o 143 aftxd_3 o field type position bits length function gp_in r [0,1] 2 sampled level on pins gp_in gp_out rw [2] 1 output level on pins gp_out table 6 : boundary scan chain sequence sequence number mnemonic pin bs type
ST70135a 27/29 electrical specifications generic dc electrical characteristics the values presented in the following table apply for all inputs and/or outputs unless otherwise specified. specifically they are not influenced by the choice between cmos or ttl levels. all voltages are referenced to v ss , unless otherwise specified, positive current is towards the device. io buffers generic dc characteristics input / output cmos generic characteristics the values presented in the following table apply for all cmos inputs and/or outputs unless otherwise specified. cmos io buffers generic characteristics *note the reference current is dependent on the exact buffer chosen and is a part of the buffer name. the available values are 2, 4 and 8ma. input/ output ttl generic characteristics the values presented in the following table apply for all ttl inputs and/or outputs unless otherwise specified. *note the reference current is dependent on the exact buffer chosen and is a part of the buffer name. the available values are 2, 4 and 8ma. symbol parameter test condition minimu m typical maximum unit i in input leakage current v in =v ss ,v dd no pull up /pull down -1 1 m a i oz tristate leakage current v in =v ss ,v dd no pull up /pull down -1 1 m a i pu pull up current v in =v ss -25 -66 -125 ma i pd pull down current v in =v dd 25 66 125 ma r pu pull up resistance v in =v ss 50 k w r pd pull down resistance v in =v dd 50 k w symbol parameter test condition minimum typical maximum unit v il low level input voltage 0.2 x v dd v v ih high level input voltage 0.8 x v dd v v hy schmitt trigger hysteresis slow edge < 1v/ m s, only for schmitx 0.8 v v ol low level output voltage i out = xma* 0.4 v v oh high level output voltage i out = xma* 0.85 x v dd v symbol parameter test conditio n minimum typical maximum unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v ilhy low level threshold, falling slow edge < 1v/ m s 0.9 1.35 v v ihhy high level threshold, rising slow edge < 1v/ m s 1.3 1.9 v v hy schmitt trigger hysteresis slow edge < 1v/ m s 0.4 0.7 v v ol low level output voltage i out = xma* 0.4 v v oh high level output voltage i out = xma* 2.4 v
ST70135a 28/29 pqfp144 package mechanical data figure 28 : package outline pqfp144 dimension millimeter inch minimum typical maximum minimum typical maximum a 4.07 0.160 a1 0.25 0.010 a2 3.17 3.42 3.67 0.125 0.135 0.144 b 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 d 30.95 31.20 31.45 1.219 1.228 1.238 d1 27.90 28.00 28.10 1.098 1.102 1.106 d3 22.75 0.896 e 0.65 0.026 e 30.95 31.20 31.45 1.219 1.228 1.238 e1 27.90 28.00 28.10 1.098 1.102 1.106 e3 22.75 0.896 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k0 (minimum), 7 (maximum) a a2 a1 b c 36 37 72 73 108 109 144 e3 d3 e1 e d1 d e 1 k b pqfp144 l l1 seating plane 0.10mm .004
ST70135a 29/29 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom - u.s.a. http ://www.st.com

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